DLS=Val_0x0, BC=Val_0x0, SP=Val_0x0, EPS=Val_0x0, PEN=Val_0x0, STOP=Val_0x0, DLAB=Val_0x0
Line Control Register
| DLS | Data Length Select When UART_LCR_EXT[DLS_E] set to 0, this field is used to select the number of data bits per character that the peripheral will transmit and receive. 0 (Val_0x0): 5 data bits per character 1 (Val_0x1): 6 data bits per character 2 (Val_0x2): 7 data bits per character 3 (Val_0x3): 8 data bits per character |
| STOP | This bit is used to select the number of stop bits per character that the peripheral will transmit and receive. If set to 0, one stop bit is transmitted in the serial data. If set to 1 and the data bits are set to 5 (UART_LCR[DLS] set to 0) one and a half stop bits are transmitted. Otherwise, 2 stop bits are transmitted. Note that regardless of the number of stop bits selected the receiver will only check the first stop bit. The STOP bit duration implemented by UART may appear longer due to IDLE time inserted between characters for some configurations and baud clock divisor values in the transmit direction; for details on IDLE time between transmitted transfers, refer to Section UART Back-to-Back Character Stream Transmission 0 (Val_0x0): 1 stop bit 1 (Val_0x1): 1.5 stop bits when UART_LCR[DLS] is 0, 2 stop bits otherwise |
| PEN | Parity Enable This bit is used to enable/disable parity generation and detection in transmitted and received serial character respectively. 0 (Val_0x0): Disable parity 1 (Val_0x1): Enable parity |
| EPS | Even Parity Select This bit is used to select between even and odd parity, when PEN set to 1. 0 (Val_0x0): An odd parity is transmitted or checked 1 (Val_0x1): An even parity is transmitted or checked |
| SP | Stick Parity This bit is used to force parity value. When PEN, EPS and SP bits are set to 1, the parity bit is transmitted and checked as logic 0. If PEN and SP are set to 1 and EPS is a logic 0, then parity bit is transmitted and checked as a logic 1. 0 (Val_0x0): Stick parity disabled 1 (Val_0x1): Stick parity enabled |
| BC | Break Control Bit This bit is used to cause a break condition to be transmitted to the receiving device. If set to 1 the UART_TX is forced to the spacing (logic 0) state. When not in Loopback mode, as determined by UART_MCR[LOOPBACK], the UART_TX is forced low until the bit is cleared. When in Loopback mode, the break condition is internally looped back to the receiver. 0 (Val_0x0): UART_TX is released for data transmission 1 (Val_0x1): UART_TX is forced to spacing state |
| DLAB | Divisor Latch Access Bit This bit is used to enable reading and writing of the Divisor Latch registers (UART_DLL and UART_DLH). This bit must be cleared after initial baud rate setup in order to access other registers. 0 (Val_0x0): Divisor Latch register is writable only when UART is not busy 1 (Val_0x1): Divisor Latch register is always readable and writable |